How does Cache work

1. instruction cache
2. data cache: L1, L2, L3
3. TLB

Data cache:
http://en.wikipedia.org/wiki/CPU_cache

Example:

The original Pentium 4 processor had a four-way set associative L1 data cache of 8 KB in size, with 64-byte cache blocks. Hence, there are 8 KB / 64 = 128 cache blocks. The number of sets is equal to the number of cache blocks divided by the number of ways of associativity, what leads to 128 / 4 = 32 sets, and hence 2⁵ = 32 different indices. There are 2⁶ = 64 possible offsets. Since the CPU address is 32 bits wide, this implies 21 + 5 + 6 = 32, and hence 21 bits for the tag field.

The original Pentium 4 processor also had an eight-way set associative L2 integrated cache 256 KB in size, with 128-byte cache blocks. This implies 17 + 8 + 7 = 32, and hence 17 bits for the tag field.^[3]